The correct statements about the Verilog code are:
- The
M1
module correctly instantiates the SubM0
module.
- The
SubM0
module correctly computes the AND of the negations of its inputs.
Thus, the correct statements are:
- The
M1
module correctly instantiates the SubM0
module.
- The
SubM0
module correctly computes the AND of the negations of its inputs.